Many electronic systems today include one or more analog-to-digital converters (ADCs) or digital-to-analog converters (DACs), and all indications are that the use of these important devices is increasing and will continue to do so for some time. This has particularly motivated manufacturers to search for ways to improve these devices, for example, by making them more powerful, faster, efficient, flexible, and less expensive.
Of present interest is the sigma delta ADC, an over sampling ADC that is also sometimes referred to as a sigma delta modulator, delta sigma ADC, and delta sigma modulator. FIG. 1 (prior art) is a schematic block diagram depicting a conventional 1st-order, N-level sigma delta ADC 10. The sigma delta ADC 10 here is a single-loop device. Multi-loop designs also exist, but the principles discussed herein are generally extendable to those in straightforward manner.
The basic principle of the multi-level sigma-delta ADC is as follows. An analog input signal (VIN) is fed into the device at a summer (Σ), and the output of the summer is coupled to an integrator (∫) (often generically termed a “loop filter” in the literature). The summer can simply be a circuit node at the input to the integrator, rather than a discrete device, and the combination is then often termed an “integration stage.” The output of the integrator is still an analog signal which is coupled to a N-level flash ADC (generically, a quantizer) that converts it into a digital signal.
In principle, the digital output signal from a N-level flash ADC can simply be in M-bit binary format where M=2(N). In practice, however, it is usually in an N-bit format where all of the bits are equally weighted, such as thermometer code. A 4-bit binary value converted into thermometer code has 15 equally weighted levels (the “all bits off” state does not require an output bit, so 2N−1 bits suffices). A value of “8” can therefore be represented in thermometer code with the bottom 8 bits set to “1” and the top 7 bits set to “0. An inverted form, where the bottom bits are set to “0” and the top bits are set to “1” may also be used.
Continuing with FIG. 1, the digital output of the N-level flash ADC is coupled to down-stream circuitry that typically performs digital filtering, decimation, and translation into a binary data word that the sigma delta ADC 10 outputs. Such circuitry is not particularly germane here and is therefore not generally discussed further.
What is of present interest is that the digital output of the N-level flash ADC is also fed back through a N-level DAC (generically, a feedback system), where it is converted back into an analog feedback signal that is provided to a second (negative) input terminal of the summer to complete a feedback loop. The N-level DAC includes a plurality of elements, such as capacitors, resistors, current sources, and the like, that must be configured to selectively release energy to produce the analog feedback signal for the summer.
Unfortunately, variation inevitably exists among these elements due to manufacturing tolerances, temperature, aging, etc. Although the absolute error from one element to another can be tightly controlled, the cumulative effect of this is termed “element mismatch” and is often significant enough that it poses a major challenge to the designers of multi-level sigma delta ADCs.
Numerous techniques are used to address element mismatch. Employing an equally weighted code helps, since the mismatch errors among the elements somewhat tends to cancel out. Other techniques include laser trimming of elements in manufacturing, calibration and recalibration processes in the field, and digital error correction in the down-stream circuitry. Dynamic element matching (DEM) algorithms, including data weighted averaging (DWA), have recently also become popular.
A sigma delta ADC can be designed with switched capacitor blocks (see e.g., U.S. Pat. No. 5,198,817) or with continuous time blocks (see e.g., U.S. Pat. No. 4,926,178). There are trade offs to selecting either approach, however, and a major one for the continuous time approach is the growth of the feedback resistors in the N-level DAC as higher numbers of levels (bits of ADC resolution) are employed. This follows from the preceding paragraphs. As the value of M increases the area required for the feedback resistors grows exponentially, yet a high bit count is desirable for many reasons. For example, it improves the power and performance of the continuous time ADC and helps with jitter insensitivity and out of band noise. [Such concepts are well documented in the art and are not elaborated on here.]
FIG. 2 (background art) is a schematic block diagram depicting a conventional 3rd-order, N-level sigma delta ADC 20. While introducing a more sophisticated type of sigma delta ADC, a number of simplifications are also used in FIG. 2 for clarity. The obvious difference here from the sigma delta ADC 10 of FIG. 1 is that the sigma delta ADC 20 here has three orders of integration with feedback summing (stylistically represented as arrowed lines for orders 22a, 22b, 22c). The integrations are performed by op amp blocks 24a, 24b, 24c (with conventional feedback capacitors, an additional signal inversion, etc. being omitted to avoid obscuring more germane features). When combined with input resistors 26a, 26b, 26c, the blocks 24a, 24b, 24c comprise non-inverting integrators. The input resistors 26a, 26b, 26c have been shown distinct from the symbols used for the blocks 24a, 24b, 24c for emphasis and to simplify the figure. The quantizing element and portions of the feedback system are collectively represented as an ADC and DAC block 28, but with the feedback resisters shown separately as feedback resisters 30a, 30b, 30c for the respective orders 22a, 22b, 22c. 
The ratios of the resistances of the feedback resisters 30a, 30b, 30c in FIG. 2 are R, 4R, 8R. In a sigma delta ADC it is usually desirable to scale the DAC feedback resistors by factors of 2 or 4. This helps, for instance, to stabilize the feedback loops. Other techniques are known aside from those using resistors (see e.g., U.S. Pat. No. 6,891,488), but since resistors can be extremely linear their use is often desirable.
If the sigma delta ADC 20 is one where N=1, the feedback resisters 30a, 30b, 30c can be simply as shown. However, to represent embodiments where N>1, the feedback resisters 30a, 30b, 30c are shown in FIG. 2 in stylized manner, and are as described in the next paragraph.
FIGS. 3a–b (background art) are schematic block diagrams that depict sets of feedback resisters 30a for exemplary 2-bit and 3-bit (M=2 and M=3) embodiments of the sigma delta ADC 20. In FIG. 3a three 3R resisters are employed, and in FIG. 3b seven 7R resisters are employed. Since it is desirable to make M as large as possible to help with a number of design parameters, the M=2 and M=3 embodiments in FIGS. 3a–b are illustrative of the principle rather than of circuits likely to be encountered. Using M=5 (or greater) is often desirable, and this means that the feedback resisters 30a, 30b, 30c for such an embodiment would each actually be implemented as 31 (25−1) resistors having value 32R, plus 31 resistors having value 4*32R, plus 31 resistors having value 8*32R.
Obviously, as M grows in value things can get out of control and limit how large M can be as a practical matter. Some noteworthy issues arising out of this are more complicated circuit design, larger circuit footprint requirements, and increased manufacturing difficulty. For the poor circuit designer this parade of horribles is further compounded because R should not be too small or power dissipation can easily also get out of control.
Accordingly, what is needed is an improved arrangement of feedback resisters in the sigma delta ADC. Such an arrangement should preferably permit the use of one or more levels, yet concurrently permit reduced resistor sizing and current consumption.
Before turning to a discussion of the present invention, we digress briefly to cover some concepts that will be helpful later. FIGS. 4a–b (prior art) are schematic diagrams depicting the relevant features of two conventional DAC designs.
FIG. 4a shows an 8-bit weighted-resister DAC. This type of DAC is widely considered to be the simplest in principle. Unfortunately, the weighted-resister DAC is an example of where principle and practicality do not well coincide and this design is rarely used in actual practice. One problem here, for example, is the complexity of accurately manufacturing the feedback resisters. Only one resister per bit is required but each has a different value (2R, 4R, . . . , 256R in FIG. 4a) and these must be precise. Furthermore, there is a wide range in the currents that then flow through the feedback resisters (a ratio of 128:1 between 2R and 256R in FIG. 4a). These factors make designing weighted-resister DACs difficult and there actual use inefficient.
FIG. 4b shows an 8-bit R-2R ladder DAC. While conceptually more complex, the R-2R ladder DAC is widely used today. The R-2R ladder DAC uses two resisters per bit, and these can all be of two values (R, 2R) which are easily manufactured and have merely a 2:1 ratio in currents. The left-most 2R resister in FIG. 4b should be noted. It is connected to ground and thus constitutes a path for “waste” current.”
With reference again to FIG. 2, it is the feedback resisters 30a, 30b, 30c there that are what would typically be implemented as the resisters (R, 2R of FIG. 4b), or less typically as the resisters (2R, 4R, . . . , 256R in FIG. 4a).
The above discussion of DACs is by no means a complete one, and is provided here only as background to the present concern of improving sigma delta ADCs. A key point to be appreciated here, however, is that the feedback resisters in the DAC sub-section significantly effect the circuit size and performance of a sigma delta ADC.